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en:hardware_guide [2026/04/26 06:41] – creado jesusen:hardware_guide [2026/04/26 06:47] (actual) – jesus
Línea 5: Línea 5:
  
 <WRAP justify> <WRAP justify>
-This is an incomplete hardware guide for the original Amstrad PCW series: 8256/8512, 9256/9512 and 10. It does not cover the PCW16.+This is an incomplete hardware guide for the original Amstrad PCW series: 8256/8512, 9256/9512, and 10. It does not cover the PCW16.
  
-Sources include "Everything you ever wanted to know..." from CP Software, John Elliott, Jacob Nevins (and their excellent web pages), Cliff Lawson (who kindly performed OCR on the original Amstrad documentation), Howard Fisher (who lent me a KeyMouse), Paul Hunt and Kevin Thacker's CPC resource, which contains Z80 and FDC information relevant to the PCW. Thanks, guys. Any additional information is always welcome.+Sources include "Everything you ever wanted to know..." by CP Software, John Elliott, Jacob Nevins (and his excellent web pages), Cliff Lawson (who kindly performed OCR on the original Amstrad documentation), Howard Fisher (who lent me a KeyMouse), Paul Hunt, and Kevin Thacker's CPC resource, which contains Z80 and FDC information relevant to the PCW. Thanks, guys. Any additional information is always welcome.
  
 Richard Fairhurst, 1996-1997 Richard Fairhurst, 1996-1997
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 <WRAP justify> <WRAP justify>
-The PCW operating system is CP/M, which is composed of two main parts.+The PCW operating system is CP/M, which consists of two main parts.
  
 The **BDOS** (Basic Disc Operating System) is the operating system code, written by Digital Research. It should remain virtually the same on any machine running CP/M. The **BDOS** (Basic Disc Operating System) is the operating system code, written by Digital Research. It should remain virtually the same on any machine running CP/M.
  
-The **BIOS** (Basic Input/Output System) provides a set of routines that access the machine's hardware and was written in the case of the PCW by Locomotive/Amstrad. The BDOS invokes BIOS routines for all screen, disk and printer operations.+The **BIOS** (Basic Input/Output System) provides a set of routines that access the machine's hardware and was written in the case of the PCW by Locomotive/Amstrad. The BDOS invokes BIOS routines for all screen, disk, and printer operations.
  
-Also relevant is the **CCP** (Console Command Processor), the interface that accepts commands entered at the A> prompt. The PCW implementation of CP/M only loads it at system startup, so it must not be overwritten.+Also relevant is the **CCP** (Console Command Processor), the interface that accepts commands entered at the A> prompt. The CP/M implementation on the PCW only loads it at system startup, so it must not be overwritten.
  
 The **TPA** (Transient Program Area) is the memory area, starting at &0100 in a 64k address space, where user programs (.COM files) are loaded and executed. The **TPA** (Transient Program Area) is the memory area, starting at &0100 in a 64k address space, where user programs (.COM files) are loaded and executed.
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 **I/O PORTS** **I/O PORTS**
  
-  * **__External hardware/FDC__**+  * **__External Hardware/FDC__**
  
 <WRAP box> <WRAP box>
  
-| &00 | I | FDC status register | +| &00 | I | FDC Status Register | 
-| &01 | I/O | FDC data register | +| &01 | I/O | FDC Data Register | 
-|&88-&8F | | Parallel ports |+|&88-&8F | | Parallel Ports |
 | &9F | I | Kempston Joystick | | &9F | I | Kempston Joystick |
 | &A0 | I | AMX Mouse. Vertical movement: b0-3 4-bit up counter, b4-7 down counter. | | &A0 | I | AMX Mouse. Vertical movement: b0-3 4-bit up counter, b4-7 down counter. |
Línea 40: Línea 40:
 | &A2 | I | AMX Mouse. Button states: b2 right, b1 middle, b0 left (0 if pressed, 1 if not). | | &A2 | I | AMX Mouse. Button states: b2 right, b1 middle, b0 left (0 if pressed, 1 if not). |
 | &A0-&A2 |  | EMR MIDI Interface | | &A0-&A2 |  | EMR MIDI Interface |
-| &A8-&AF |  | Hard disk | +| &A8-&AF |  | Hard Drive | 
-| &C8-&CF | I/O | Fax link interface ([[es:puerto_serie|CPS8256]] compatible circuit). |+| &C8-&CF | I/O | Fax Link Interface (compatible circuit with [[en:serial_port|CPS8256]]). |
 | &D0-&D4 |  | Kempston Mouse (similar to AMX) | | &D0-&D4 |  | Kempston Mouse (similar to AMX) |
-| &DF | I | MasterScan: b0 ink under the scan head. | +| &DF | I | MasterScan: ink b0 under the scan head. | 
-| &E0 | I | Cascade/Spectravideo joystick. b4 right, b3 up, b2 left, b1 fire, b0 down. | +| &E0 | I | Cascade/Spectravideo Joystick. b4 right, b3 up, b2 left, b1 fire, b0 down. | 
-| &E0-&EF | I/O | [[es:puerto_serie|Serial ports]] (click for more info) |+| &E0-&EF | I/O | [[en:serial_port|Serial Ports]] (click for more info) |
 </WRAP> </WRAP>
  
-  * **__Internal ports__**+  * **__Internal Ports__**
  
 <WRAP box> <WRAP box>
  
-| &F0 | W | Select bank for &0000 | +| &F0 | OUT | Select bank for &0000 | 
-| &F1 | W | Select bank for &4000 | +| &F1 | OUT | Select bank for &4000 | 
-| &F2 | W | Select bank for &8000 | +| &F2 | OUT | Select bank for &8000 | 
-| &F3 | W | Select bank for &C000. Normally, &87. | +| &F3 | OUT | Select bank for &C000. Usually, &87. | 
-| &F4 | W | b7-b4: when set, forces memory reads to access the same bank as writes for &C000, &0000, &8000 and &4000 respectively | +| &F4 | OUT | b7-b4: when set, forces memory reads to access the same bank as writes for &C000, &0000, &8000, and &4000 respectively | 
-| &F4 | I | Same as &F8, with the condition that b3-0 is reset when reading the port. Therefore, read to reactivate interrupts. | +| &F4 | I | Same as &F8, provided that b3-0 is reset upon reading the port. Therefore, read to reactivate interrupts. | 
-| &F5 | W | Roller RAM address. b7-5: bank (0-7). b4-1: address / 512. | +| &F5 | OUT | Roller RAM address. b7-5: bank (0-7). b4-1: address / 512. | 
-| &F6 | W | Vertical screen position | +| &F6 | OUT | Vertical screen position | 
-| &F7 | W | b7: reverse video. b6: screen enable. | +| &F7 | OUT | b7: inverse video. b6: screen enable. | 
-| &F8 | W | 0 end boot, 1 reset, 2/3/4 connect FDC to NMI/standard interrupts/none, 5/6 set/clear FDC terminal count, 7/8 turn screen on/off (for external video), 9/10 turn disk motor on/off, 11/12 turn beep on/off | +| &F8 | OUT | 0 end boot, 1 reset, 2/3/4 connect FDC to NMI/standard interrupts/none, 5/6 set/clear FDC terminal count, 7/8 turn screen on/off (for external video), 9/10 turn disk motor on/off, 11/12 turn beep on/off | 
-| &F8 | I | b6: 1-line return, reading twice in a row indicates frame return. b5: FDC interrupt. b4: indicates 32-line screen. b3-0: 300 Hz interrupt counter: remains at 1111 until reset by in a,(&F4)(see above). |+| &F8 | I | b6: 1-line flyback, reading twice in a row indicates frame flyback. b5: FDC interrupt. b4: indicates 32-line screen. b3-0: 300 Hz interrupt counter: remains at 1111 until reset with in a,(&F4)(see above). |
 | &FC-&FD |  | Parallel port (PCW9512) | | &FC-&FD |  | Parallel port (PCW9512) |
 | &FC | I/O | Dot matrix printer data | | &FC | I/O | Dot matrix printer data |
-| &FD | W | Dot matrix printer commands |+| &FD | OUT | Dot matrix printer commands |
 | &FD | I | Dot matrix printer status. b7 safety bar (0 out), b2 paper found. | | &FD | I | Dot matrix printer status. b7 safety bar (0 out), b2 paper found. |
 </WRAP> </WRAP>
  
 <WRAP justify> <WRAP justify>
-Unlike the CPC, the PCW uses the standard Z80 method for accessing I/O ports. The port is stored as a (single byte) number in C and an instruction such as out (c),a is used, or it is passed as part of the out (&port),a instruction.+Unlike the CPC, the PCW uses the standard Z80 method for accessing I/O ports. The port is stored as a (single byte) number in C and an instruction like out ( c ),a is used [insert number], or it is passed as part of the out (&port),a instruction.
 </WRAP> </WRAP>
  
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 <WRAP justify> <WRAP justify>
-Interrupts occur 300 times per second, or 6 times per frame (as on the CPC), at the 2 scan lines of the frame flyback and every 52 lines thereafter. Frame flyback can be detected by reading port &F8 twice consecutively. Only if b6 is set each time is the PCW in frame flyback.+Interrupts occur 300 times per second, or 6 times per frame (as in the CPC), at 2 scan lines of the frame flyback and every 52 lines thereafter. Frame flyback can be detected by reading port &F8 twice consecutively. Only if b6 is set both times is the PCW in frame flyback.
  
-The PCW clock speed is 3.4 MHz, lower than a 4 MHz CPU. However, video hardware access slows down memory access up to the first 128k (banks 0-7). The BIOS interrupt is also slow and should be disabled for time-critical operations where tasks like keyboard scanning and disk access are not required.+The PCW clock speed is 3.4 MHz, lower than a 4 MHz CPU. However, video hardware access slows down memory access to the first 128k (banks 0-7). The BIOS interrupt is also slow and should be disabled for time-critical operations where tasks such as keyboard scanning or disk access are not required.
 </WRAP> </WRAP>
  
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 | | &3800-&3FFF:| character set| | | &3800-&3FFF:| character set|
 |3| &0000-&3FEF:| BIOS, BDOS| |3| &0000-&3FEF:| BIOS, BDOS|
-| | &3FF0-&3FFF:| DMA keyboard map|+| | &3FF0-&3FFF:| Keyboard DMA map|
 |4| &0000-&00FF:| workspace and BIOS/BDOS jumps| |4| &0000-&00FF:| workspace and BIOS/BDOS jumps|
 | | &0100-&3FFF:| TPA| | | &0100-&3FFF:| TPA|
Línea 104: Línea 104:
 | | &3000-&3FFF:| CP/M workspace| | | &3000-&3FFF:| CP/M workspace|
 |8| &0000-&3FFF:| CCP, hash tables, data buffers| |8| &0000-&3FFF:| CCP, hash tables, data buffers|
-|9-16| &0000-&3FFF:| RAM disk (M: drive)|+|9-16| &0000-&3FFF:| RAM disk (drive M:)|
 </WRAP> </WRAP>
  
 <WRAP justify> <WRAP justify>
-Roller RAM and screen memory can be stored in any of banks 0 to 7. Therefore, video circuitry access requirements slow down access to code/data in these banks.+Roller RAM and screen memory can be stored in any of the banks 0 to 7. Therefore, the access requirements of the video circuitry slow down access to code/data in these banks.
  
 Any bank can be mapped into any of the four 16k segments of the Z80 address space via ports &F0-&F3. In CP/M, the following (named) configurations are standard: Any bank can be mapped into any of the four 16k segments of the Z80 address space via ports &F0-&F3. In CP/M, the following (named) configurations are standard:
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 <WRAP justify> <WRAP justify>
-By sending the bank number (with b7 set) to one of the ports &F0-&F3, that bank is selected for reading and writing. By sending the bank number for writing to b0-2 of a port and the bank for reading to b4-b6 (with b7 clear), separate banks are assigned for reading and writing: this can only be used for the first 8 banks.+By sending the bank number (with b7 set) to one of the ports &F0-&F3, that bank is selected for both reading and writing. By sending the bank number for writing to b0-2 of a port and the bank for reading to b4-b6 (with b7 reset), separate banks are assigned for reading and writing: this can only be used for the first 8 banks.
  
 As an example of read/write access, to map bank 5 into memory from &4000, you would use ld a,&85: out (&F1),a. As an example of read/write access, to map bank 5 into memory from &4000, you would use ld a,&85: out (&F1),a.
Línea 131: Línea 131:
  
 <WRAP justify> <WRAP justify>
-La pantalla PCW en los modelos de 50 Hz (no estadounidenses) tiene una resolución de 90 x 32 caracteres o 720 x 256 píxeles. Cada línea de píxel puede comenzar en cualquier dirección dentro de los primeros 128 kB de memoria: la dirección de cada línea se almacena en un área de memoria de 512 bytes conocida como RAM de rodillo. Por defecto, la RAM de rodillo se encuentra en &3600 (asignada a &B600) en el banco 2, pero esto puede cambiarse mediante el puerto &F5. Contiene 256 direcciones consecutivas, almacenadas en el formato habitual de Z80, primero el byte bajo: b16-14 controlan en qué banco se encuentra la línea, b13-3 la dirección en el banco (en unidades de 16 bytes) y b2-0 el desplazamiento. Por lo tanto, una dirección de RAM de rodillo bbbxxxxxxxxxxxyyy indica banco bbb, dirección 00xxxxxxxxxxx0yyy.+The PCW screen on 50Hz (non-US) models has a resolution of 90 x 32 characters or 720 x 256 pixels. Each pixel line can start at any address within the first 128 kB of memory: the address of each line is stored in a 512-byte memory area known as Roller RAM. By default, the Roller RAM is located at &3600 (mapped to &B600) in bank 2, but this can be changed via port &F5. It contains 256 consecutive addresses, stored in the usual Z80 format, low byte first: b16-14 control which bank the line is in, b13-3 the address in the bank (in units of 16 bytes), and b2-0 the offset. Thus, a Roller RAM address bbbxxxxxxxxxxxyyy indicates bank bbb, address 00xxxxxxxxxxx0yyy.
  
-Cada línea tiene una longitud de 720 bytes, no de 90. Esto se debe a que el PCW ocupa cada octavo byte a partir de la dirección indicada por la RAM de rodillos. De esta manera, se pueden intercalar ocho líneas de pantalla de la siguiente manera para facilitar la escritura de caracteres (suponiendo una disposición consecutiva de la RAM de rodillos): +Each line has a length of 720 bytes, not 90. This is because the PCW takes every eighth byte starting from the address indicated by the Roller RAM. In this way, eight screen lines can be interleaved as follows to facilitate character writing (assuming a consecutive Roller RAM layout):
-</WRAP> +
- +
-  (a+0) (a+8)  (a+16) ...  +
-  (a+1) (a+9)  (a+17)  +
-  (a+2) (a+10) (a+18)  +
-  (a+3) (a+11) (a+19)  +
-  (a+4) (a+12) (a+20)  +
-  (a+5) (a+13) (a+21)  +
-  (a+6) (a+14) (a+22)  +
-  (a+7) (a+15) (a+23) +
- +
-La posición vertical de la pantalla en el monitor se puede alterar incrementando o disminuyendo el puerto &F6. +
- +
-**MAPEO DEL TECLADO** +
- +
-<WRAP justify> +
-El teclado del PCW se asigna directamente a los últimos 16 bytes del banco 3, incluso con las interrupciones deshabilitadas. Cada tecla se refleja en un bit en los bytes &3FF0-&3FFA. +
-</WRAP> +
- +
-<WRAP box> +
-| b7: | k2 k1 [+] . , espacio VXZ del< alt |  +
-| b6: | k3 k5 1/2 / MNBC bloquear k. |  +
-| b5: | k6 k4 shift ; KJFDA enter |  +
-| b4: | k9 k8 k7 ¤ LHGS tab f8 |  +
-| b3: | pegar copiar # PIYTWQ [-] |  +
-| b2: | f2 cortar regresar [ OURE parar puede |  +
-| b1: | k0 ptr ] - 9 7 5 3 2 extra |  +
-| b0: | f4 salir del> = 0 8 6 4 1 f6 |  +
-|      | &3FF0 &3FF1 &3FF2 &3FF3 &3FF4 &3FF5 &3FF6 &3FF7 &3FF8 &3FF9 &3FFA |  +
-</WRAP> +
- +
-<WRAP justify> +
-Los bytes &3FFB-&3FFF reflejan el teclado de forma diferente e incompleta. Estos bytes también son utilizados por KeyMouse de Creative Technology (en su modo estándar de MicroDiseño) y el teclado Teqniche de 102 teclas para proporcionar funcionalidad adicional, lo que genera algunas incompatibilidades. Entre las asignaciones más interesantes se encuentran las siguientes: +
-</WRAP> +
- +
-<WRAP box> +
-| &3FFB | Teclado estándar | b7-b0 sin usar (0) | +
-|       | KeyMouse         | b6-b0 contador de movimiento horizontal. | +
-| &3FFC | KeyMouse    | b7-b6 bits altos del contador de movimiento vertical. | +
-| &3FFD | Todos            | b7 siempre establecido; b6 estado actual de SHIFT LOCK | +
-|       | los teclados estándar | b3-b0 teclas de cursor, b4 tecla de matriz | +
-|       | KeyMouse         | b3-b0 bits bajos del contador de movimiento vertical. | +
-| &3FFE | KeyMouse      | b7 botón izquierdo, b6 botón derecho. | +
-</WRAP> +
- +
-<WRAP justify> +
-The PCW screen on 50Hz (non-US) models has a resolution of 90 x 32 characters or 720 x 256 pixels. Each pixel line can start at any address within the first 128 kB of memory: the address for each line is stored in a 512-byte area of memory known as Roller RAM. By default, Roller RAM is located at &3600 (mapped to &B600) in bank 2, but this can be changed via port &F5. It contains 256 consecutive addresses, stored in the usual Z80 format, low byte first: b16-14 control which bank the line is in, b13-3 the address in the bank (in units of 16 bytes), and b2-0 the offset. Thus, a Roller RAM address bbbxxxxxxxxxxxyyy indicates bank bbb, address 00xxxxxxxxxxx0yyy. +
- +
-Each line is 720 bytes long, not 90. This is because the PCW takes every eighth byte starting from the address indicated by the Roller RAM. In this way, eight screen lines can be interleaved as follows to facilitate character writing (assuming a consecutive Roller RAM layout):+
 </WRAP> </WRAP>
  
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 <WRAP justify> <WRAP justify>
-The PCW keyboard is mapped directly to the last 16 bytes of bank 3, even with interrupts disabled. Each key is reflected in a bit in bytes &3FF0-&3FFA.+The PCW keyboard is mapped directly to the last 16 bytes of bank 3, even with interrupts disabled. Each key is reflected by a bit in bytes &3FF0-&3FFA.
 </WRAP> </WRAP>
  
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 | b7: | k2 k1 [+] . , space VXZ del< alt |  | b7: | k2 k1 [+] . , space VXZ del< alt | 
-| b6: | k3 k5 1/2 / MNBC shift lock k. | +| b6: | k3 k5 1/2 / MNBC k. lock | 
 | b5: | k6 k4 shift ; KJFDA enter |  | b5: | k6 k4 shift ; KJFDA enter | 
 | b4: | k9 k8 k7 ¤ LHGS tab f8 |  | b4: | k9 k8 k7 ¤ LHGS tab f8 | 
Línea 216: Línea 167:
  
 <WRAP justify> <WRAP justify>
-Bytes &3FFB-&3FFF reflect the keyboard differently and incompletely. These bytes are also used by Creative Technology's KeyMouse (in its standard MicroDesign mode) and the Teqniche 102-key keyboard to provide additional functionality, leading to some incompatibilities. Among the most interesting mappings are the following:+Bytes &3FFB-&3FFF reflect the keyboard differently and incompletely. These bytes are also used by the Creative Technology KeyMouse (in its standard MicroDesign mode) and the Teqniche 102-key keyboard to provide additional functionality, which leads to some incompatibilities. Among the most interesting mappings are the following:
 </WRAP> </WRAP>
  
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 | &3FFB | Standard keyboard | b7-b0 unused (0) | | &3FFB | Standard keyboard | b7-b0 unused (0) |
 |       | KeyMouse         | b6-b0 horizontal movement counter. | |       | KeyMouse         | b6-b0 horizontal movement counter. |
-| &3FFC | KeyMouse    | b7-b6 high bits of the vertical movement counter. |+| &3FFC | KeyMouse    | b7-b6 high bits of vertical movement counter. |
 | &3FFD | All              | b7 always set; b6 current state of SHIFT LOCK | | &3FFD | All              | b7 always set; b6 current state of SHIFT LOCK |
 |       | standard keyboards | b3-b0 cursor keys, b4 matrix key | |       | standard keyboards | b3-b0 cursor keys, b4 matrix key |
-|       | KeyMouse         | b3-b0 low bits of the vertical movement counter. | +|       | KeyMouse         | b3-b0 low bits of vertical movement counter. | 
-| &3FFE | KeyMouse      | b7 left button, b6 right button. |+| &3FFE | KeyMouse         | b7 left button, b6 right button. |
 </WRAP> </WRAP>
- 
- 
  
en/hardware_guide.1777185714.txt.gz · Última modificación: por jesus