en:hardware:perifericos:cps8256_interfaz_paralelo_centronics_y_serie_rs232c []

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  <div class="pcw-title-ultra retro-text-green"> A> CPS8256 (Centronics Parallel and RS232C Serial Interface) </div>
  
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        <div class="img-frame"><a href="#pcps"><img src="/lib/exe/fetch.php?media=hardware:perifericos:interface_cps8256_amstrad.jpg"></a><span class="img-label">General Overview</span></div>
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  <div class="pcw-subtitle-box">Description, Context and History</div>
  <div class="content-body">
    <p>Officially marketed by <strong>Amstrad plc</strong> in 1985 concurrently with the launch of the Amstrad PCW 8256 and PCW 8512 models, the <strong>CPS8256</strong> interface stands as the most critical official peripheral for communication expansion on this platform. The baseline design of the PCW range deliberately lacked general-purpose communication ports, relying exclusively on proprietary connection links routed solely to its bundled monitor unit and dedicated matrix printer. The CPS8256 was conceived to address this isolation, enabling for the first time the direct hookup of telephone modems, serial mice, plotters, and data streams to third-party dot-matrix, daisy-wheel, or early laser printers.</p>
    <p>Regarding historical preservation documentation, a persistent misconception circulated in 1980s computer magazines claiming that the parallel port implementation violated the Centronics standard because it processed pure 8-bit word lengths instead of 7-bit channels. Low-level hardware analysis has proven this to be an outright myth: the physical port complies 100% with the standard electrical line signals and communications protocol. The real conflict stemmed from Locomotive Software's bundled word processor, <em>LocoScript</em>. It utilized an internal character map and proprietary formatting control characters, resulting in unreadable gibberish outputs unless text documents were explicitly exported or converted into a plain vanilla ASCII standard format before being printed via the parallel interface.</p>
    <p>This extension drastically broke the isolated ecosystem of the PCW, allowing asynchronous connections with mainframes or IBM-compatible PCs using transfer suites like <em>LocoLink</em> or terminal protocols like <em>Kermit</em>, thus cementing the computer as an open business workstation rather than a dead-end typing machine.</p>
  </div>
  <div class="pcw-subtitle-box">Hardware Architecture and Silicon Components</div>
  <div class="content-body">
    <p>From an electronic engineering perspective, the CPS8256 houses a set of Zilog logic family integrated circuits (or licensed clones) internally, perfectly coordinated to manage asynchronous I/O operations without causing overhead to the main Z80 CPU of the computer:</p>
    <ul>
      <li><strong>Z80 DART (Dual Asynchronous Receiver/Transmitter) / Z80 SIO:</strong> This is the communication core of the device. Physically, it features two independent data transmission/reception channels. In Amstrad's layout, <strong>Channel A</strong> is fully wired to control the serial port under the RS-232C standard, while <strong>Channel B</strong> was cleverly repurposed to monitor and sequence the status lines, control signals, and handshaking of the Centronics parallel port.</li>
      <li><strong>Z80 CTC (Counter/Timer Circuit):</strong> This timer IC is used exclusively as a dedicated programable baud rate generator (Baud Rate Generator). Its independent internal channels process the clock frequencies required to synchronize the internal registers of the Z80 DART, allowing stable data transmission ratios to be established.</li>
      <li><strong>Voltage Converter Subsystem:</strong> The lateral expansion bus of the Amstrad PCW only distributes +5V and +12V power supply lines. Since the international RS-232C specification mandates symmetric negative voltage thresholds to encode serial logical data states (preventing background noise), the CPS8256 incorporates an internal inverter/voltage converter circuit dedicated to generating the <strong>-12V</strong> rail required for line signaling.</li>
    </ul>
  </div>

  <div class="pcw-subtitle-box">Z80 Input/Output (I/O) Port Mapping</div>
  <div class="content-body">
    <p>The CPS8256 interface decodes on the system bus by occupying a fixed range of 8 addressable ports spanning from <code>0E0h</code> to <code>0E7h</code>. The hardware register layout breaks down as follows:</p>
    <table class="tech-table">
      <thead>
        <tr>
          <th>Port (Hex)</th>
          <th>Port (Dec)</th>
          <th>Access</th>
          <th>System Function and Register Target</th>
        </tr>
      </thead>
      <tbody>
        <tr>
          <td><strong><code>0E0h</code></strong></td>
          <td>224</td>
          <td>R / W</td>
          <td><strong>Z80 DART (Channel A) - Data Register:</strong> Reads incoming characters from the serial buffer (Rx) and writes data to be transmitted (Tx).</td>
        </tr>
        <tr>
          <td><strong><code>0E1h</code></strong></td>
          <td>225</td>
          <td>R / W</td>
          <td><strong>Z80 DART (Channel A) - Control Register:</strong> Writes to point to internal registers (WR0-WR5) and reads status registers (RR0-RR1).</td>
        </tr>
        <tr>
          <td><strong><code>0E2h</code></strong></td>
          <td>226</td>
          <td>Write Only</td>
          <td><strong>Centronics Parallel Port - Output Register (Data Latch):</strong> Stores and latches the 8-bit data byte onto physical lines D0-D7 for the printer.</td>
        </tr>
        <tr>
          <td><strong><code>0E3h</code></strong></td>
          <td>227</td>
          <td>Read Only</td>
          <td><strong>Centronics Parallel Port - Status Register:</strong> Real-time read of the physical hardware control lines (Busy, /Ack, Paper Empty, Select).</td>
        </tr>
        <tr>
          <td><strong><code>0E4h</code></strong></td>
          <td>228</td>
          <td>Write Only</td>
          <td><strong>Z80 CTC (Channel 0) - Transmitter Timer:</strong> Sets the time constant defining the Baud Rate for serial transmission (Tx).</td>
        </tr>
        <tr>
          <td><strong><code>0E5h</code></strong></td>
          <td>229</td>
          <td>Write Only</td>
          <td><strong>Z80 CTC (Channel 1) - Receiver Timer:</strong> Sets the time constant defining the Baud Rate for serial reception (Rx).</td>
        </tr>
        <tr>
          <td><strong><code>0E6h</code></strong></td>
          <td>230</td>
          <td>—</td>
          <td>Line reserved by decoding hardware / Unused by the Amstrad standard design.</td>
        </tr>
        <tr>
          <td><strong><code>0E7h</code></strong></td>
          <td>231</td>
          <td>Write Only</td>
          <td><strong>Z80 CTC (Channel 3) - General Control Register:</strong> Initializes the operating mode of the counter circuits and hardware timer interrupts.</td>
        </tr>
      </tbody>
    </table>
  </div>

  <div class="pcw-subtitle-box">Internal Register Structure of the Z80 DART (Port 0E1h)</div>
  <div class="content-body">
    <p>For direct low-level programming (e.g., in Z80 assembly language, bypassing CP/M BIOS calls), the CPS8256 control port operates sequentially. The internal register number to be accessed is written to <code>0E1h</code>, and in the following I/O clock cycle, the configuration value is sent to or read from that same port. Critical preservation bit functions are detailed below:</p>
    <ul>
      <li><strong>WR3 (Write Register 3 - Receiver Configuration):</strong> Bits 7 and 6 define the received data word length (<code>11</code> = 8 bits, <code>10</code> = 7 bits, <code>01</code> = 6 bits, <code>00</code> = 5 bits). Bit 5 enables hardware auto-flow control via the CTS/RTS lines, and Bit 0 physically activates the receiver logic (Rx Enable).</li>
      <li><strong>WR4 (Write Register 4 - Transmission Parameters):</strong> Bits 7 and 6 control the clock multiplier factor (invariably set to <code>01</code> for the PCW design). Bits 3 and 2 define the Stop Bits (<code>11</code> = 2 bits, <code>10</code> = 1 bit). Bit 1 activates the parity bit (1 = Even, 0 = Odd), and Bit 0 activates or deactivates parity checking.</li>
      <li><strong>WR5 (Write Register 5 - Transmitter Configuration):</strong> Bit 7 controls the physical DTR line state. Bits 6 and 5 establish the word length for transmitted data (<code>11</code> = 8 bits, <code>10</code> = 7 bits). Bit 3 enables data transmission (Tx Enable), and Bit 1 directly controls the output RTS line.</li>
      <li><strong>RR0 (Read Register 0 - Line Status Register):</strong> Allows transfer verification via polling. Bit 7 monitors the Break condition. Bit 5 reflects the logical state of the CTS line, Bit 4 shows RI (Ring Indicate), and Bit 3 tracks DCD (Carrier Detect). Bit 2 switches to a high state (1) when the hardware transmit buffer is empty and ready, while Bit 0 indicates that an incoming character is waiting in the receiver buffer to be read.</li>
      <li><strong>RR1 (Read Register 1 - Error Register):</strong> Stores accumulated logical errors. Bit 6 detects Framing Errors, Bit 5 catches hardware receiver overrun errors (Rx Overrun Error), and Bit 4 flags logical Parity Errors.</li>
    </ul>
  </div>
  <div class="pcw-subtitle-box">Port Connections and Pinouts</div>
  <div class="content-body">
    <p>The CPS8256 exposes two internationally standardized physical connectors wired according to Amstrad's electronic design specifications:</p>
    
    <p><strong>1. Serial Port (DB25 Male Connector - DTE Standard Configuration):</strong></p>
    <table class="tech-table">
      <thead>
        <tr>
          <th>DB25 Pin</th>
          <th>RS-232C Signal</th>
          <th>Flow (PCW)</th>
          <th>Electrical Line Function</th>
        </tr>
      </thead>
      <tbody>
        <tr>
          <td>Pin 1</td>
          <td>GND (Shield)</td>
          <td>—</td>
          <td>Protective Ground (Chassis mass / cable shielding reference).</td>
        </tr>
        <tr>
          <td>Pin 2</td>
          <td>TXD (Transmit Data)</td>
          <td>Output</td>
          <td>Serial transmission line for asynchronous binary data.</td>
        </tr>
        <tr>
          <td>Pin 3</td>
          <td>RXD (Receive Data)</td>
          <td>Input</td>
          <td>Serial reception line for asynchronous binary data.</td>
        </tr>
        <tr>
          <td>Pin 4</td>
          <td>RTS (Request To Send)</td>
          <td>Output</td>
          <td>Hardware flow control request sent by the PCW to transmit data.</td>
        </tr>
        <tr>
          <td>Pin 5</td>
          <td>CTS (Clear To Send)</td>
          <td>Input</td>
          <td>Signal from the peripheral authorizing the PCW to send data.</td>
        </tr>
        <tr>
          <td>Pin 6</td>
          <td>DSR (Data Set Ready)</td>
          <td>Input</td>
          <td>Confirmation that the remote device/modem is powered on and ready.</td>
        </tr>
        <tr>
          <td>Pin 7</td>
          <td>GND (Signal Ground)</td>
          <td>—</td>
          <td>Common ground reference for all digital data signals.</td>
        </tr>
        <tr>
          <td>Pin 8</td>
          <td>DCD (Data Carrier Detect)</td>
          <td>Input</td>
          <td>Telephone carrier tone detection line (used by modems).</td>
        </tr>
        <tr>
          <td>Pin 20</td>
          <td>DTR (Data Terminal Ready)</td>
          <td>Output</td>
          <td>Signal confirming that the Amstrad PCW is online and operative.</td>
        </tr>
        <tr>
          <td>Pin 22</td>
          <td>RI (Ring Indicator)</td>
          <td>Input</td>
          <td>Telephone ring detection line indicator.</td>
        </tr>
      </tbody>
    </table>

    <p><strong>2. Parallel Port (36-pin Amphenol Centronics Female Connector):</strong></p>
    <ul>
      <li><strong>Pin 1:</strong> <code>/STROBE</code> control signal (Active-low output. Synchronization pulse emitted by the PCW to warn the printer that data on bus D0-D7 is valid and must be latched).</li>
      <li><strong>Pins 2 to 9:</strong> 8-bit parallel Data Bus (Logical signal lines <code>D0</code> to <code>D7</code>).</li>
      <li><strong>Pin 10:</strong> <code>/ACK</code> control signal (Active-low input. Pulse sent by the printer indicating that it has successfully processed the previous byte).</li>
      <li><strong>Pin 11:</strong> <code>BUSY</code> signal (Active-high input. Line kept at 1 by the printer when it is offline, processing data, or its buffer is full, ordering the PCW to halt transmission).</li>
      <li><strong>Pin 12:</strong> <code>PE</code> error signal (Paper Empty - Active-high input notifying the physical absence of paper in the external printer).</li>
      <li><strong>Pin 13:</strong> <code>SLCT</code> status signal (Select - Active input confirming that the peripheral device is selected and online).</li>
      <li><strong>Pins 19 to 30:</strong> Logic ground returns to common ground (Signal Ground / GND).</li>
    </ul>
  </div>

  <div class="pcw-subtitle-box">Operating System Support and Emulator Integration</div>
  <div class="content-body">
    <ul>
      <li><strong>Dynamic BIOS Patching:</strong> If the CPS8256 is physically connected to the lateral expansion bus during cold boot, the startup routine stored in the system load block of the <strong>CP/M Plus</strong> operating system automatically recognizes the hardware. The BIOS dynamically alters the official welcome message on the CRT monitor, appending the string: <code>(SIO/Centronics add-on)</code>.</li>
      <li><strong>MAIL232 Communications Tool:</strong> The original system utility floppy disk distributed officially by Amstrad included the <code>MAIL232.COM</code> executable. This utility interacted directly with the CPS8256 serial registers, effectively converting the computer into a compatible terminal for early BBS systems.</li>
      <li><strong>CP/M Box (by Habi / Habisoft):</strong> Habi's emulator fully intercepts all read and write operations directed to logical ports <code>0E0h-0E7h</code>. It allows users to map and redirect all this data stream into modern host system physical/virtual COM ports, or route the Centronics parallel data directly into text files or Windows LPT print queues.</li>
      <li><strong>Joyce (by John Elliott):</strong> Replicates the internal logic of the Z80 CTC integrated circuit and the synchronous behavior of the Z80 DART mapped to its original hardware address space with absolute cycle-accurate precision.</li>
    </ul>
  </div>

  <div class="pcw-subtitle-box">Documentation and Downloads</div>
  <div class="content-body">
    <ul>
      <li></html>{{hardware:descargas:Manual_CPS8256_French.pdf|RS232C Serial Interface Manual in French}}<html> </html>{{:otros:francia.jpg?nolink&25|}}<html></li>
      <li></html>{{hardware:descargas:Manual_CPS8256_English.pdf|RS232C Serial Interface Manual in English}}<html> </html>{{:otros:reino_unido.jpg?nolink&25|}}<html></li>
    </ul>
  </div>
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