The Intergem Disk Drive Interface from [[en:companias:Dynamic Data Technology|Dynamic Data Technology]] is an adapter for Shugart-standard external disk drives on the PCW. It generates its own /RDY signal, meaning there is no need to use disk units that inherently feature it. The power connector is the same as the one found on Acorn BBC computers.
Top ViewBottom ViewThis peripheral was developed by Ray Alker. It is an interface that fits inside the slot or bay of the second disk drive of a PCW8256 (the original plate covering the bay must be removed). It includes a connector for an 80-track, 5.25" Shugart-standard drive. It features a rather unusual connector suited for 5.25" drives mounted on Acorn BBC computers (it is highly recommended not to use the Amstrad PCW's internal power supply for this purpose, as it is not powerful enough).
Connecting the interface is fairly straightforward (remember to perform any connection with the computer turned off, and in this specific case, as we have to handle its internal parts, we recommend completely unplugging it from the mains). Inside, we will find two connectors: one connection that goes to the power supply and the other to the data ribbon cable of the PCW itself at drive B:.
Its chips and integrated circuits are a mystery: as we have seen, connecting a Shugart-compatible unit is simply a matter of connectors. From what has been deduced, the reason for using these Acorn BBC-based connectors is simply because the company only had access to that specific system.
Despite the initial mystery noted in historical columns, modern hardware preservation and comprehensive reverse-engineering documentation have fully unmasked Ray Alker's electronic design for this internal adapter PCB:
READY / pin 4)—which is strictly mandated by the Amstrad motherboard's onboard NEC µPD765A floppy disk controller (FDC)—the Intergem board had to synthesize this feedback pulse artificially./MOTOR_ON or /DRVSEL1 lines), the incoming electrical pulse triggers one of the stages on the 74LS123 chip. Coupled with an onboard resistor-capacitor (RC) network that dictates a fixed time constant delay, the monostable circuit generates an artificial lag of a few hundred milliseconds. This delay mimics the mechanical latency required for a real hardware motor to accelerate and stabilize its rotation. Once this brief timer expires, the chip's conmuted output automatically drives the /RDY line low (0V), fooling the CP/M Plus BIOS and enabling flawless disk data transfers without throwing the critical Read Error message.