====== Zilog Z80 ======

===== Info =====

^  {{:hardware:imagenes:Z80-CPU.png|}}  ^^  

This processor was built following a project that involved two years of hard work. It was created by Federico Faggin after he undertook the development of a new processor that would be more economical and compatible with the Intel 8080, but superior in performance.
 
This 8-bit little-endian processor was launched on the market in July 1976, offered at an affordable price and challenging the then-famous Intel 8080. Its compatibility with the 8080 meant that applications developed for the Intel processor could be executed on the Z80, including the CP/M operating system.
 
Compared to the Intel 8080, the Z80 introduced several improvements, leading it to be considered an expansion of the Intel chip. The Z80 featured an expanded instruction set, the inclusion of a couple of new registers, and the simplification of necessary auxiliary devices (clock, memory, etc.). It entered the market with great impact, ultimately sweeping the Intel 8080 aside.

^  {{:hardware:imagenes:Z80-architecture.gif|}}  ^^  
^__Z80 CPU Internal Organization__^^

This processor is considered a hybrid between an accumulator architecture and a general-purpose register architecture. It can be categorized within the register-memory type processors.

__General characteristics__

The Z80 has an 8-bit data bus but handles 16-bit instructions and addresses (allowing it to address up to 64 KB). Alignment is not required. It has 22 registers (18 are 8-bit and 4 are 16-bit). Twelve of them can be used in pairs (providing 6 16-bit registers). The clock frequency varies by version; it began with a 2.5 MHz clock cycle, with later models reaching 20 MHz. The Z80A, the popular version, operated at 3.58 MHz (4 MHz factory rating). It features 6 different addressing modes.

__Registers__

   * A is the accumulator register; B, C, D, E, H, and L are 8-bit general-purpose registers. They can form 16-bit pairs (BC, DE, HL).
   * A', B', C', D', E', H', and L' (Alternative Bank): A replica of the original register bank.
   * I (Interrupt Vector Register): Stores the high-order byte of the interrupt vector table's start address.
   * R (Refresh Register): Stores the memory block to be refreshed.
   * F (Flag Register): Stores condition bits.
   * IX, IY: Index registers.
   * SP (Stack Pointer): Points to the stack.
   * PC (Program Counter): Tracks the program execution.
   * F (Condition Bits Register): Includes H (Half-carry, indicating a carry from the low nibble to the high nibble) and P (Parity bit)

__Connection diagram__

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