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===== AMSTRAD CPS8256 TECHNICAL REFERENCE =====

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The sources for this document are two PD text files, DART.DOC (by SJ Dibble) and AMS-SIO.DAT, which cover only the serial port. Information on the parallel port and any other serial/parallel interfaces would be appreciated.

Richard Fairhurst, 1997
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**PORT ADDRESSES**

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The CPS8256 uses the following I/O addresses. For reference, equivalent ports on the Amstrad, Pace, and Cirkit interfaces for the CPC are included in brackets.
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| &E0 | (&FADC) | DART Data |
| &E1 | (&FADD)	| DART Control |
| &E2 | (&FADE)	| DART Data (Port B) |
| &E3 | (&FADF)	| DART Control (Port B) |
| &E4 | (&FBDC)	| 8253 Counter 0 |
| &E5 | (&FBDD)	| 8253 Counter 1 |
| &E6 | (&FBDE)	| unused |
| &E7 | (&FBDF)	| 8253 Write Mode Word |
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**BAUD RATES**

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To set the transmission speed, send &36 to port &E7 and two values from the table (in the order shown) to port &E4. To set the reception speed, replace &36 with &76. These values are obtained with the 8253 CTC connected at 1.84375 MHz.

Note that the 8250 is only reliable at speeds up to 9600 baud. For higher speeds, it should be replaced with a 16550AF chip, which is compatible with the 8250. (Thanks to Rob Scott for this info).
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| 31250 | &00, &04 |
| 19200	| &00, &07 |
| 9600	| &00, &0D |
| 7200	| &00, &11 |
| 4800	| &00, &1A |
| 3600	| &00, &23 |
| 2400	| &00, &34 |
| 2000	| &00, &3F |
| 1800	| &00, &45 |
| 1200	| &00, &68 |
| 600	| &00, &D0 |
| 300	| &01, &A0 |
| 200	| &02, &71 |
| 150	| &03, &41 |
| 110	| &04, &70 |
| 75	| &06, &83 |
| 50	| &09, &C4 |
| 45	| &0A, &D9 |
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**DART REGISTERS**

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Other control functions involve programming the DART. To write a value to a register, first send the register number and then the new value to &E1. To read a value, send the register number and you can then input it from the same port.
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  * **__Write Register 0__**


| &18: | reset port |
| &38: | reset error bits |

  * **__Write Register 3__**


| b7 and b6: | Rx data bits (11 8 bits, 10 7, 01 6, 00 5) |
| b5: | hardware handshake via RTS/CTS |
| b4 to b1: | must be 0 |
| b0: | enable Rx data line |

  * **__Write Register 4__**


|b7 and b6: |DART clock mode (set to 01)|
|b5 and b4: |unused (set to 0)|
|b3 and b2: |stop bits (11 2 bits, 10 1, 01 1.5, 00 illegal)|
|b1: |parity type (1 even, 0 odd)|
|b0: |parity check on/off|

  * **__Write Register 5__**


|b7: |DTR enabled/disabled|
|b6: |Tx data bits (11 8 bits, 10 7, 01 6, 00 5)|
|b4: |send interrupt|
|b3: |enable Tx data line|
|b2: |unused|
|b1: |RTS enabled/disabled|
|b0: |unused|

  * **__Read Register 0__**


|b7: |interrupt received|
|b6: |unused|
|b5: |CTS|
|b4: |ring indicator|
|b3: |DCD (data carrier detect)|
|b2: |transmit buffer ready|
|b1: |interrupt related|
|b0: |receive character available|

  * **__Read Register 1__**


|b7: |unused|
|b6: |framing error|
|b5: |Rx overrun error|
|b4: |parity error|
|b3 to b1: |unused|
|b0: |all sent|
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