NEC µPD765 Floppy Disk Controller (FDC)
The NEC µPD765 is an iconic floppy disk controller (FDC) from the 1980s, fundamental to the computer architecture of that era. In the Amstrad ecosystem, it was natively integrated into models such as the CPC 664, CPC 6128, and the PCW series, as well as being used in the DDI-1 external interface for the CPC 464.
Main Technical Specifications
- Capacity: Can control up to 4 floppy disk units simultaneously.
- Density: Supports single density (FM, IBM 3740) and double density (MFM, IBM System 34) formats, including double-sided recording.
- Operation Modes: Allows data transfers via DMA (Direct Memory Access) or via interrupts (Non-DMA).
- Commands: Executes a set of 15 commands for reading, writing, formatting, and seeking.
Use in Amstrad Systems (CPC/PCW)
In Amstrad systems, the chip communicates with the processor through specific I/O ports:
- Port &FB7E: Main Status Register (read-only).
- Port &FB7F: Data Register (read/write) for sending commands and receiving results.
- Port &FA7E: Floppy disk motor control (On/Off) via an external flip-flop.
Bit b10 of the address port is reset, as the FDC is considered an expansion, even if it is an internal chip. Bit b7 is reset to select the FDC. Bits b8 and b0 are used to select the specific operation mode. All other bits must be set to 1 to avoid conflicts.
Legacy and Documentation
This chip was not only the heart of storage in Amstrad systems, but it was also the standard in early IBM PCs, the ZX Spectrum +3, and the Sega SC-3000.
Accessing the µPD765
The Main Status Register signals when the FDC is ready to send/receive the next byte through the Data Register.
The Data Register is used to write commands and parameters, read/write data bytes, and receive result bytes. These three operations are:
- Command Phase: A command consists of a command byte (which eventually includes the MT, MF, and SK bits) and up to 8 parameter bytes.
- Execution Phase: During this phase, actual data (if any) is transferred. Typically, these are the data bytes from read/write sectors, except for the format track command, in which case 4 bytes are transferred per sector. During data transfers between the FDC and the processor, the FDC must be serviced every 26 µs (in MFM mode with CPC timing) or the FDC will terminate the FDC command.
- Result Phase: Returns up to 7 result bytes (depending on the command) containing status information. During the result phase, all result bytes must be read. The FDC will not accept a new command until all result bytes have been read.
Note: The Recalibrate and Seek Track commands do not return result bytes directly. Instead, the program must wait until the Main Status Register indicates that the command is complete, and then it must send a Sense Interrupt Status command to finish the Seek/Recalibrate command.
Documentation
In the following links, you can view all the documentation (PDF) regarding the chip.