This is an incomplete hardware guide for the original Amstrad PCW series: 8256/8512, 9256/9512 and 10. It does not cover the PCW16.

Sources include “Everything you ever wanted to know…” from CP Software, John Elliott, Jacob Nevins (and their excellent web pages), Cliff Lawson (who kindly performed OCR on the original Amstrad documentation), Howard Fisher (who lent me a KeyMouse), Paul Hunt and Kevin Thacker's CPC resource, which contains Z80 and FDC information relevant to the PCW. Thanks, guys. Any additional information is always welcome.

Richard Fairhurst, 1996-1997

The PCW operating system is CP/M, which is composed of two main parts.

The BDOS (Basic Disc Operating System) is the operating system code, written by Digital Research. It should remain virtually the same on any machine running CP/M.

The BIOS (Basic Input/Output System) provides a set of routines that access the machine's hardware and was written in the case of the PCW by Locomotive/Amstrad. The BDOS invokes BIOS routines for all screen, disk and printer operations.

Also relevant is the CCP (Console Command Processor), the interface that accepts commands entered at the A> prompt. The PCW implementation of CP/M only loads it at system startup, so it must not be overwritten.

The TPA (Transient Program Area) is the memory area, starting at &0100 in a 64k address space, where user programs (.COM files) are loaded and executed.

Unlike the CPC, the PCW uses the standard Z80 method for accessing I/O ports. The port is stored as a (single byte) number in C and an instruction such as out ©,a is used, or it is passed as part of the out (&port),a instruction.

Interrupts occur 300 times per second, or 6 times per frame (as on the CPC), at the 2 scan lines of the frame flyback and every 52 lines thereafter. Frame flyback can be detected by reading port &F8 twice consecutively. Only if b6 is set each time is the PCW in frame flyback.

The PCW clock speed is 3.4 MHz, lower than a 4 MHz CPU. However, video hardware access slows down memory access up to the first 128k (banks 0-7). The BIOS interrupt is also slow and should be disabled for time-critical operations where tasks like keyboard scanning and disk access are not required.

The PCW 8256 has 16 banks of 16k each. 512k and expanded machines obviously contain more. The default content is:

Roller RAM and screen memory can be stored in any of banks 0 to 7. Therefore, video circuitry access requirements slow down access to code/data in these banks.

Any bank can be mapped into any of the four 16k segments of the Z80 address space via ports &F0-&F3. In CP/M, the following (named) configurations are standard:

By sending the bank number (with b7 set) to one of the ports &F0-&F3, that bank is selected for reading and writing. By sending the bank number for writing to b0-2 of a port and the bank for reading to b4-b6 (with b7 clear), separate banks are assigned for reading and writing: this can only be used for the first 8 banks.

As an example of read/write access, to map bank 5 into memory from &4000, you would use ld a,&85: out (&F1),a.

La pantalla PCW en los modelos de 50 Hz (no estadounidenses) tiene una resolución de 90 x 32 caracteres o 720 x 256 píxeles. Cada línea de píxel puede comenzar en cualquier dirección dentro de los primeros 128 kB de memoria: la dirección de cada línea se almacena en un área de memoria de 512 bytes conocida como RAM de rodillo. Por defecto, la RAM de rodillo se encuentra en &3600 (asignada a &B600) en el banco 2, pero esto puede cambiarse mediante el puerto &F5. Contiene 256 direcciones consecutivas, almacenadas en el formato habitual de Z80, primero el byte bajo: b16-14 controlan en qué banco se encuentra la línea, b13-3 la dirección en el banco (en unidades de 16 bytes) y b2-0 el desplazamiento. Por lo tanto, una dirección de RAM de rodillo bbbxxxxxxxxxxxyyy indica banco bbb, dirección 00xxxxxxxxxxx0yyy.

Cada línea tiene una longitud de 720 bytes, no de 90. Esto se debe a que el PCW ocupa cada octavo byte a partir de la dirección indicada por la RAM de rodillos. De esta manera, se pueden intercalar ocho líneas de pantalla de la siguiente manera para facilitar la escritura de caracteres (suponiendo una disposición consecutiva de la RAM de rodillos):

El teclado del PCW se asigna directamente a los últimos 16 bytes del banco 3, incluso con las interrupciones deshabilitadas. Cada tecla se refleja en un bit en los bytes &3FF0-&3FFA.

Los bytes &3FFB-&3FFF reflejan el teclado de forma diferente e incompleta. Estos bytes también son utilizados por KeyMouse de Creative Technology (en su modo estándar de MicroDiseño) y el teclado Teqniche de 102 teclas para proporcionar funcionalidad adicional, lo que genera algunas incompatibilidades. Entre las asignaciones más interesantes se encuentran las siguientes:

The PCW screen on 50Hz (non-US) models has a resolution of 90 x 32 characters or 720 x 256 pixels. Each pixel line can start at any address within the first 128 kB of memory: the address for each line is stored in a 512-byte area of memory known as Roller RAM. By default, Roller RAM is located at &3600 (mapped to &B600) in bank 2, but this can be changed via port &F5. It contains 256 consecutive addresses, stored in the usual Z80 format, low byte first: b16-14 control which bank the line is in, b13-3 the address in the bank (in units of 16 bytes), and b2-0 the offset. Thus, a Roller RAM address bbbxxxxxxxxxxxyyy indicates bank bbb, address 00xxxxxxxxxxx0yyy.

Each line is 720 bytes long, not 90. This is because the PCW takes every eighth byte starting from the address indicated by the Roller RAM. In this way, eight screen lines can be interleaved as follows to facilitate character writing (assuming a consecutive Roller RAM layout):

The PCW keyboard is mapped directly to the last 16 bytes of bank 3, even with interrupts disabled. Each key is reflected in a bit in bytes &3FF0-&3FFA.

Bytes &3FFB-&3FFF reflect the keyboard differently and incompletely. These bytes are also used by Creative Technology's KeyMouse (in its standard MicroDesign mode) and the Teqniche 102-key keyboard to provide additional functionality, leading to some incompatibilities. Among the most interesting mappings are the following: